1. Field of the Invention
The invention relates to a semiconductor memory device, more particularly to a high-speed cell-sensing unit for a semiconductor memory device.
2. Description of the Related Art
Referring to FIGS. 1 and 2, a cell 11 of a conventional random access memory device is associated with a complementary pair of bit lines (BIT, /BIT) 121, 122, and a word line 13. A voltage sense amplifier 10, such as a current-mirror voltage sense amplifier, is formed from five transistors (M1), (M2), (M3), (M4), (M5), and has input terminals (V1), (V2) connected to the bit lines 121, 122, and output terminals (V3), (V4)
To illustrate the operation of the known voltage sense amplifier 10, it is assumed that the bit lines 121, 122 are pre-charged to a same certain voltage (Vp) prior to operation of the voltage sense amplifier 10, and that a data "1" is stored in the cell 11 of the memory device. When the pre-charging voltage is deactivated, and the word line 13 is activated, the bit line (BIT) 121 will be maintained at a high "1" logic state due to a charging action thereon by the cell 11. On the other hand, the bit line (/BIT) 122 will discharge to a low "0" logic state. At this time, when the control signal (.phi.) is active, the amplifier 10 begins to operate. Assuming that the transistors (M1), (M2), (M3), (M4) of the amplifier 10 initially operate at the saturation region such that the voltages at the input terminals (V1), (V2) are approximately equal to (Vp), the voltages at the output terminals (V3), (V4) are approximately equal to (V.sub.DD -V.sub.thP), where (V.sub.thP) is the threshold voltage of the transistors (M3), (M4).
As the bit line (/BIT) 122 discharges to the low "0" logic state, the voltage at the input terminal (V2) decreases. According to the following Equation (I), which is the drain current equation for an MOS transistor operating in the saturation region: EQU Id=k1/2(V.sub.GS -V.sub.th).sup.2 (I),
a decrease in the voltage at the input terminal (V2) will result in a corresponding decrease in the gate-source voltage (V.sub.GS) of the transistor (M2), and in the drain current of the transistor (M2). At the same time, the drain current of the transistor (M4) will decrease, thereby resulting in a corresponding decrease in the gate-source voltage (V.sub.GS) of the transistor (M4) and in an increase in the gate voltage (V4) of the transistor (M4). Since the transistors (M3), (M4) are in a current-mirror configuration, the decrease in the drain current of the transistor (M4) will result in a corresponding decrease in the drain currents of the transistors (M3), (M1). However, since the bit line (BIT) 121 is continuously charged by the cell 11, the input terminal (V1) can be maintained at the high "1" logic state. Further reduction in the drain current of the transistor (M1) will eventually result in operation of the transistor (M1) in the triode region. According to the following Equation (II), which is the drain current equation for an MOS transistor operating in the triode region: EQU Id=k[(V.sub.GS -V.sub.th)V.sub.DS -1/2V.sub.GS.sup.2 ] (II),
when the voltage at the input terminal (V1) and thus, the gate-source voltage (VGS) of the transistor (M1), remains unchanged, a reduction in the drain current of the transistor (M1) will result in a corresponding reduction in the drain-source voltage (VDS) of the transistor (M1), thereby leading to a reduction in the voltage at the output terminal (V3). Therefore, when the voltage at the input terminal (V2) continues to drop, the drain currents of the transistors (M4), (M3), (M1) will be reduced correspondingly so that the voltage at the output terminal (V3) will also drop.
When the bit line (/BIT) 122 continues to discharge to the low "0" logic state, the drain current of the transistor (M2) will approach 0 A. The transistors (M2), (M4) will eventually be turned off, and the voltage at the output terminal (V4) will approach the supply voltage (V.sub.DD). With the transistor (M3) turned off, and the transistor (M1) turned on, the voltage at the output terminal (V3) will be approximately equal to 0 volt. Therefore, it can be understood from the foregoing description and from Equations (I) and (II) that current is largest at the initial stage of operation of the entire system, and is subsequently and gradually reduced to approximately 0 A.
Recent progress in semiconductor manufacturing techniques has resulted in smaller component sizes, higher densities, and in higher operating frequencies. In order to maintain component reliability and reduce power consumption, a reduction in the supply voltage is unavoidable. However, a lower supply voltage will result in the following drawbacks for the aforesaid conventional memory device that incorporates the current-mirror voltage sense amplifier 10:
Upon pre-charging of the bit lines 121, 122, the maximum voltage thereat will be equal to the supply voltage (V.sub.DD) minus the threshold voltage (V.sub.thN) of the associated NMOS bit-line load 141, 142. Thus, the maximum voltage at the input terminals (V1), (V2) of the amplifier 10 will be approximately equal to 1/2V.sub.DD, which is ideal for optimum voltage gain. However, when the supply voltage (V.sub.DD) is reduced, the maximum voltage at the bit lines 121, 122 will be correspondingly lowered because the threshold voltages (V.sub.thN) of the NMOS bit-line loads 141, 142 have fixed values. Thus, the noise margin of the cell 11 will be poorer, and the stability and soft error immunity of the cell 11 during a read cycle of the memory device will be adversely affected.
It has been proposed heretofore to employ PMOS transistors as bit-line loads instead of NMOS transistors during low supply voltage applications. However, when PMOS bit-line loads are in use, the maximum voltage at the bit lines 121, 122 will be approximately equal to the supply voltage (V.sub.DD), thereby affecting adversely the gain of the amplifier 10. Moreover, it is noted that the area of the cell 11 is very small as compared to that of the bit lines 121, 122, and that a very large parasitic capacitance is present across the bit lines 121, 122. Thus, charging and discharging of the bit lines 121, 122 during a read cycle of the memory device require a relatively long amount of time, thereby affecting adversely the formation of a sufficient voltage difference between the input terminals (V1, V2) of the amplifier 10 for enabling the latter to generate a full swing output signal, and further affecting adversely the operating efficiency of the amplifier 10. This drawback is further aggravated during low supply voltage applications.
Furthermore, large amounts of current are generated during the initial stages of operation of the amplifier 10. Due to the relatively long discharge time of the bit lines 121, 122, the amplifier 10 operates under high current conditions for a relatively long period of time, thereby resulting in relatively large power consumption.